Noise Improvement of a-Si Microbolometers by the Post-Metal Annealing Process.

To realize high-resolution thermal images with high quality, it is essential to improve the noise characteristics of the widely adopted uncooled microbolometers. In this work, we applied the post-metal annealing (PMA) process under the condition of deuterium forming gas, at 10 atm and 300 °C for 30 min, to reduce the noise level of amorphous-Si microbolometers. Here, the DC and temperature coefficient of resistance (TCR) measurements of the devices as well as 1/f noise analysis were performed before and after the PMA treatment, while changing the width of the resistance layer of the microbolometers with 35 µm or 12 µm pixel. As a result, the microbolometers treated by the PMA process show the decrease in resistance by about 60% and the increase in TCR value up to 48.2% at 10 Hz, as compared to the reference device. Moreover, it is observed that the noise characteristics are improved in inverse proportion to the width of the resistance layer. This improvement is attributed to the cured poly-silicon grain boundary through the hydrogen passivation by heat and deuterium atoms applied during the PMA, which leads to the uniform current path inside the pixel.

Temperature Dependence of Low Frequency Noise in Silicon on Insulator Tunneling Field Effect Transistor.

In this work, noise mechanism of a tunneling field-effect transistor (TFET) on a silicon-on-insulator substrate was studied as a function of temperature. The results show that the drain current and subthreshold slope increase with increase in temperature. This temperature dependence is likely caused by the generation of greater current flow owing to decreased silicon band gap and leakage. Further, the TFET noise decreases with increase in temperature. Therefore, the effective tunneling length between the source and the channel appears to decrease and Poole-Frenkel tunneling occurs.

Effective Schottky barrier lowering of NiGe/p-Ge(100) using Terbium interlayer structure for high performance p-type MOSFETs.

Ultra-low contact resistance at the interface between NiGe and p-Ge, i.e., NiGe/p-Ge was achieved by introducing terbium (Tb) as an interlayer in forming NiGe using Tb/Ni/TiN structure. The contact resistance value obtained using the circular transmission line model for an 8-nm thick Tb interlayer sample was 7.21 × 10-8 Ω·cm2, which is two orders of magnitude less than that of reference sample (without the Tb interlayer) of 7.36 × 10-6 Ω·cm2. The current-voltage characteristics were studied at a temperature range of -110 ~ 25 °C to determine the effective Schottky barrier height (eSBH). An eSBH of 0.016 eV was obtained for the 8-nm thick Tb interlayer. Various Tb interlayer thicknesses were selected to study their effect on the contact resistance. The Tb interlayer surface and structural properties were characterized using FESEM, XRD, XPS, TEM, and SIMS analyses.

Gate Voltage Dependence of Low Frequency Noise in Tunneling Field Effect Transistors.

In this paper, the dependency of low frequency noise as a function of the gate voltage was examined for tunneling field effect transistors (TFETs). When the level of gate voltage is low, the tunneling width of the TFETs is large. Thus, electrons move via the trap instead of tunneling directly. On the other hand, when the level of gate voltage is high, the tunneling width of the TFETs becomes narrow. Thus, when the gate voltage is low, the noise level of TFETs is high because electrons pass through the trap. However, when the gate voltage is high, electrons pass directly from valence band of source to conduction band of drain, so the noise level is low. Finding the voltage suitable for this TFET is important to determine the optimum conditions for generating BTBT when measuring TFETs and to reduce noise.

Investigation of Positive Bias Temperature Instability Characteristics of Fully Depleted Silicon on Insulator Tunneling Field Effect Transistor with High-k Dielectric Gate Stacks.

The positive bias temperature instability (PBTI) characteristics of fully depleted silicon on insulator (FD-SOI) tunneling field effect transistor (TFET) are investigated in comparison with those of metal oxide semiconductor field effect transistor (MOSFET) fabricated with the same technology process. Unlike some of the previously reported studies, in which the PBTI lifetime of TFET is much longer than that of MOSFET, in this study, the PBTI lifetime of TFET is found to be shorter than that of MOSFET. This result is very interesting, because degradation of electrical parameters of TFET is mainly affected by local traps near the source junction rather than global traps in the channel region. Large degradation of the electrical parameters of TFET due to PBTI stress would result from large fluctuation of the vertical electric field caused by traps near the source junction. This electric field fluctuation near the local region in TFET has more impact on electrical parameter degradation than channel conductivity fluctuation in MOSFET. Therefore, to improve the reliability characteristics of TFET, evaluation of PBTI characteristics and improvement of the quality of gate oxide near the source junction are essential.